This invention relates to a temporary bus master for use in a digital system having asynchronously communicating sub-systems.
An important issue in defining the architecture of a complex digital system is how to provide control over communication among individual sub-systems. Such individual sub-systems are generally subject to local timing constraints that make it impractical to rely on a global clock to synchronize all communication from one sub-system to another. This applies not only where each sub-system is housed on a separate printed circuit board as in an exemplary case of a motherboard with circuitry defining a central processing unit and another board with circuitry defining a peripheral controller, but also where each sub-system is embodied in an individual integrated circuit on the same printed circuit board. In either case, an asynchronous communication protocol is essential for coordinated operation of the individual sub-systems.
Numerous matters need to be considered in defining a complete asynchronous communication protocol. For example, one major consideration is how, within a sender, it can be determined at any point in time whether the sender can apply signals on its output to send a message. Another example of such a major consideration is how, within a receiver, it can be determined at any point in time whether signals at its input represent a message. The relative simplicity or complexity of a protocol depends in part on the approach taken in interconnecting the sub-systems. There are various such interconnection approaches that can be considered in terms of a spectrum. At one end of the spectrum is an approach that is sometimes referred to as point-to-point interconnection; at the opposite end of the spectrum is another such approach that is sometimes referred to as a shared asynchronous communication bus. In a point-to-point interconnection at one end of the spectrum, there is no sharing of either conductors used for data items to be communicated or conductors used for control signals by which communication is coordinated. In a fully shared asynchronous communication bus at the opposite end of the spectrum, all the conductors are shared. A middle approach involves sharing of conductors used for data items, but point-to-point interconnection of conductors used for communication-control signals.
As general matter, it is desirable to minimize the number of conductors used for interconnecting sub-systems. One reason for desiring to minimize the number of such conductors relates to packaging, particularly limitations on the number of pins that can be used for an integrated circuit chip. In this regard, a microprocessor that is used in many personal computers and commonly called an 8086 microprocessor has only forty pins. To use this microprocessor in its maximum mode, it is connected to a separate bus controller called an 8288 bus controller. When the 8086 microprocessor is used with the 8288 bus controller, some of the precious few pins of the 8086 microprocessor are reallocated to participate in other desirable functions. One of these reallocated pins is used in the minimum mode of operation for a bus control signal called Address Latch Enable (ALE). The foregoing example is representative of a general rule that pins are at a premium, especially for large-scale integrated circuits.
One well known protocol can briefly be called request/acknowledge protocol. In implementing this protocol, a first conductor carries request signals that in accord with this protocol are applied to the first conductor only by a slave, and a second conductor carries acknowledge signals that in accord with this protocol are applied to the second conductor only by a master.
When a slave seeks to participate in communication with the master, whether to send or receive a parallel-by-bit data item such as an 8-bit byte, or a 16-bit word, or the like, the slave asserts the request signal. Upon detecting that the request signal is asserted, the master asserts the acknowledge signal at least once to indicate it is ready to receive or send the data item. In a burst mode of communication, the slave continuously asserts the request signal throughout an interval during which a series of data items are communicated, one data item per acknowledge signal. In an interlock mode of communicating, the slave asserts the request signal for each data item.
The request/acknowledge protocol can be used for communication between as few as two integrated circuits interconnected in accord with the point-to-point approach, and for communication over a shared bus.
Where this request/acknowledge protocol is followed in a fully shared bus in which all conductors of the bus are shared, two bus slaves connected to the bus cannot directly communicate with each other. Rather, every bus slave communicates directly only with the bus master. Some systems include an arrangement in which a Direct Memory Access (DMA) controller is provided. Such a DMA controller and a microprocessor can time share the task of being the bus master. In such a system, the microprocessor surrenders control over the bus to the DMA controller for such an indefinite interval of time as is required for a communication task, and whenever that task is finished, the DMA controller surrenders control over the bus back to the microprocessor.
While the microprocessor controls the bus, the DMA controller does not participate in any communication between the microprocessor and a bus slave. Likewise, while the DMA controller controls the bus, the microprocessor does not participate in any communication between the DMA controller and a bus slave.
Certain block communication tasks are difficult to accomplish rapidly and economically with any previously known architecture. In general terms, such a block communication task involves multiple sub-systems in which a first one of the sub-systems needs to receive a leading sub-block of data items that also needs to be received by another one of the sub-systems, and further in which the first sub-system also needs to participate, whether as a sender or receiver, in communication of a trailing sub-block of the same block. An example of such a circumstance involves a disk drive controller. A disk drive controller performs numerous tasks incident to the writing and reading of data onto and from a disk. One such function is to provide serial-by-bit communication with the disk, which entails local timing constraints and particular format constraints dictated by the particular specifications of the disk drive and the way in which data is stored in sectors within tracks, and so forth.
For numerous reasons, the serial-by-bit communication with the disk is block organized wherein every access to the disk entails a data transfer of at least one block and sometimes an integral number of blocks, with a block typically being coextensive with the storage capacity of a sector. Another such function is a serializer/deserializer (SERDES) function. While writing data to disk, the SERDES function involves converting parallel-by-bit data items such as 8-bit bytes into a serial-by-bit signal for use in writing data on the disk. While reading data from the disk, the SERDES function involves converting the serial-by-bit signal read from the disk to parallel-by-bit data items. Numerous formatter chips are well known and commercially available for performing the foregoing and associated functions as an interface device for the disk drive.
Another function of a disk drive controller is to provide buffer memory. Numerous buffer manager chips and memory chips are well known and commercially available for providing such buffer memory.
In some circumstances, it is desirable for the disk drive controller to provide an additional function that entails two main steps, one being to generate data items and the other being to append the generated data items as a trailing sub-block within a block. This is particularly desirable for a high performance disk drive controller for a large capacity disk drive such as an optical disk drive.
A requirement for generating such data items can arise in implementing a disk addressing technique for avoiding access to sectors of the disk that have been found defective. In such a case, the generated data items define a linked list. Alternatively, or in addition, another requirement for generating such data items can arise in implementing an error correction technique. In such a case, the data items generated during a write operation are error correction codes (ECC codes). Such ECC codes that form a trailing sub-block are data-dependent items; that is, their values depend upon the particular data defining the leading sub-block. During a read operation, in which an error-correction technique such as Reed-Solomon error-correction is involved, there needs to be generated first a set of syndromes based on a block of data items read from the disk, and then, based on such syndromes, there needs to be generated other data items for use in making corrections to any errors in the leading sub-block.
In any such case, the complexities of the functions involved may make it essential to provide at least three integrated circuit chips such as a buffer manager chip, an ECC chip, and a formatter chip that need to communicate with each other. In considering a point-to-point interconnection at one end of the spectrum as a candidate architectural feature of such a system, the following problems appear. First, the ECC chip would have to be connected as the middle element of a tandem arrangement, and would have to have one set of pins for communicating with the buffer manager chip and another set of pins for communicating with the formatter chip. Second, the ECC chip would have to have a large first-in, first out (FIFO) memory. In particular, that FIFO memory would have to be deep enough so that during a block transfer for a disk write operation it could hold an entire block including the leading sub-block of data items that it would pass on to the formatter after it had computed the data-dependent ECC codes for the trailing sub-block. Third, this would involve a block latency.
Considering a bus structure as a candidate architectural feature of such a system presents a complex problem as to providing other architectural features that become necessary to support use of a shared bus for coordinated communication. The issues that need to be resolved in defining the architecture for this system involve both writing to disk and reading from disk. With respect to writing to disk, there are issues as to providing a way within the formatter and a way within the ECC generator to determine the particular points in time that the data bus carries parallel-by-bit data items sent by the buffer manager to define the leading sub-block of a block to be written to disk. Further, a way has to be provided to determine when the ECC generator can and must start sending the sequence of ECC codes to the formatter. The complexity of this problem is exacerbated because it can not be determined with a sufficient degree of precision, either within the buffer manager chip or within the formatter chip, the time at which the ECC chip is ready to send the first of the sequence of ECC items. With respect to reading from disk, there are issues as to providing a way within the buffer manager and a way within the ECC generator to determine the particular points in time that the data bus carries parallel-by-bit data items sent by the formatter to define the leading sub-block of a block to be written to disk. In sum, considering a bus structure as a candidate architectural feature of such a system presents a complex problem, particularly in the light of needs for a high data transfer rate, and for economy of use of integrated circuit pins and FIFO memories.